A TDD scheme is a two-way transmission scheme that allocates uplink and downlink alternately in a time sequence in one frequency band. The TDD scheme has higher efficiency than a Frequency Division Duplex (hereinafter, referred to as FDD) scheme that allocates different frequencies to uplink and downlink, and also has a characteristic to be suitable for transmitting asymmetric or bursting applications. According to this advantage, the TDD scheme is being applied to various communication fields such as the portable Internet in 2.3 GHz band and the like.
A communication field using the TDD scheme may include human body communication recently being studied.
The human body communication transmits a signal by using a human body rather than by using a wire. In the human body communication, the electrical signal is transmitted through the human body without using electric wires since the human body acts as a conductive medium. As personal portable electronic devices are recently diversified, the human body communication is in the limelight in that data transmission and reception between the electronic devices can be easily realized. In addition, the human body communication can be used to transmit results of measurement from various devices, which measure human health states, to other devices such as a computer and the like. Like this, its application fields may be infinite.
On the other hand, a CDR circuit is a device that generates a clock signal, which is synchronized with an input data signal, and recovers a data signal, which is distorted in course of transmission using the clock signal.
The CDR circuit is used in a wide range of various communication fields including human body communication, a disk drive, and the like.
In general, the CDR circuit is implemented with a Phase Lock Loop (PLL). The CDR circuit detects, through a phase detector, a phase difference between an output frequency of a variable oscillator, which has an oscillating frequency variable in response to a control signal input, and an input data signal of the variable oscillator, and then controls the variable oscillator to reduce the phase difference, thereby generating a clock signal having a frequency synchronized with an input data signal.